The system level block diagram of the Evaluation Tool design is shown in the below figure. Xilinx PetaLinux flow is used to create and integrate the software components, including Linux kernel and drivers.

Xilinx Vivado IPI flow is used to create the hardware design which is partitioned between the processing system (PS), RFDC IP, and programmable logic (PL). The Evaluation Tool allows user to configure the operation of the RF-ADCs & RF-DACs including the associated clocking system, to perform signal generation and capture using RFDACs & RFADCs and to perform RF metrics computation on signal capture for input test signals. The Evaluation Tool consists of a ZCU111 evaluation board and a custom graphical user interface (UI) installed on a Windows host machine. The Evaluation Tool serves as a platform for Xilinx customers to evaluate the Zynq® UltraScale+™ RFSoC features and helps them to accelerate the product design cycle. The design demonstrates the capabilities and performance of the RFdc (RF-ADC and RF-DAC) available in Zynq® UltraScale+™ RFSoC devices. This document provides the steps to build and run the RFSoC RF Data Converter Evaluation Tool.

The UG provides the list of device features, software architecture and hardware architecture.

Zynq UltraScale+ ZCU111 RFSoC RF Data Converter TRD user guide, UG1287.

How to build all the Evaluation Tool components based on the provided source files via detailed step-by-step tutorials.Īdditional material not covered in this tutorial.

How to setup the ZCU111 evaluation board and run the Evaluation Tool.

This tutorial contains information about: A detailed information about the three designs can be found from the following pages. In the subsequent versions the design has been split into three designs based on the functionality. As mentioned above,in the 2018.2 version of the design, all the features were the part of a single monolithic design.

Xilinx vivado download 2018.2